Evidence
Measured on real hardware
The run-level detail behind the latency figures: how each number was measured, on what, with the attribution behind it — including the gaps we log rather than hide.
The reference kernel result
Measured December 2025 · GIDE benchmark corpus
A single closed-form continuous-time (CfC) cell — the reference inference kernel — completes one forward pass in 0.767 µs on average.
Methodology
Arithmetic mean over 10,000 sequential inference calls after 1,000 warmup iterations, nanosecond-precision monotonic timing with compiler barriers.
Environment
x86_64 with AVX2; compiled with zig cc (Clang) at -O3 -march=native -ffast-math on the Zig 0.14.0-dev toolchain current at the time of measurement. The run predates our hardware-attribution harness, so the exact CPU model behind this figure is not on record — a gap we log rather than hide.
Cross-platform re-runs
ARM (attributed)
A fully hardware-attributed run on a Neoverse-N2 (Clang 21.1.0) measures 0.75 µs mean with 0.76 µs p99 — within a few percent of the reference figure.
x86 (committed)
A committed x86 sweep measures the same cell at 0.81 µs mean — about 6% above the reference figure, on a host that is likewise not on record.
The deployed controller
Measured July 2026 · GIDE benchmark corpus
A deployed end-to-end controller measures ≈52 µs p50 and ≈99 µs p99 per control cycle — the figures to cite for whole-controller latency, not the reference kernel above. It clears the same 10 ms real-time budget by roughly 190× at p50 and roughly 100× at p99. Under a real-time budget the tail is what decides whether the loop holds, so the p99 margin is the one to weigh; neither margin is a proven bound.
Methodology
Percentiles over 50,000 consecutive control cycles after 1,000 warmup cycles, timed end to end across the whole controller rather than around a single inference call — the latency a control loop actually has to fit.
Environment
A shared 4-vCPU x86 development container (2.8 GHz Xeon) under variable load, so the absolute figures are noisy: run to run the controller moves between roughly 44 and 52 µs at p50, and 77 and 99 µs at p99. The two figures published above are the slowest on record and the margins are derived from them, but the honest reading of the result is tens of microseconds on this class of hardware rather than a tight constant. Maximum-latency outliers on that host are scheduler jitter rather than controller cost, which is why p50 and p99 are the percentiles we publish.
Artifacts
The benchmark harness, per-run logs, and a hardware-attribution ledger live in the GIDE repository; nightly CI re-runs the suite on attributed runners and publishes the results.